The present invention relates to a semiconductor device and a manufacturing method thereof. In particular, the invention pertains to a technology effective when applied to a semiconductor device having a strained silicon layer.
There is a technology of forming a strain-relaxed silicon-germanium layer (SiGe layer) over a semiconductor substrate made of silicon and then forming a strained silicon layer by the epitaxial growth of a silicon layer over this silicon-germanium layer. This strained silicon layer has a higher electron mobility than that of an ordinary silicon layer so that by forming a channel of an MISFET (Metal Insulator Semiconductor Field Effect Transistor) in the strained silicon layer, the mobility of electrons flowing through the channel can be heightened, which leads to an improvement in the electrical properties of the MISFET (for example, as described in IEDM Technical Digest, p 23-26 (2002)).
As a technology of forming a strained silicon layer over a silicon-germanium layer, that of forming a silicon-germanium layer which has a small film thickness, is free of penetration dislocations, and has a flat surface on an atomic level is disclosed, for example, in Japanese Unexamined Patent Publication No. 2002-217413. According to this technology, misfit dislocations exist on the interface between a silicon substrate and the silicon-germanium layer.
In Japanese Unexamined Patent Publication No. 2004-39762, disclosed is a technology of increasing the moving speed of carriers at the end of a source, thereby achieving the speed-up of an MISFET. Described specifically, this technology is, in an MISFET having a strained SiGe layer formed over a buried insulator film, a gate electrode formed over this strained SiGe layer via a gate insulating film, and a source region and a drain region formed on both sides of the gate electrode, to maximize the Ge concentration of the channel region (under the center of the gate electrode), while minimizing the Ge concentration of the source region and drain region.
In Japanese Unexamined Patent Publication No. 2000-031491, disclosed is a technology of forming an SiGe strain-applied layer as thin as about 200 nm over an SOI (Silicon On Insulator) substrate, thereby preventing threading dislocations of the SiGe strain-applied layer, generation of cracks and worsening of surface property.
In Japanese Unexamined Patent Publication No. Hei 9 (1997)-321307, disclosed is a technology of forming a high-quality strained silicon layer having a sufficient strain without damaging a reducing effect of a floating capacity brought by an SOI structure. Described specifically, after formation of an SiGe layer, as a strain-applied semiconductor layer, over a silicon substrate, a buried oxide layer is formed to divide this SiGe layer into upper and lower regions and the upper SiGe layer is thinned. In order to reduce the defects such as dislocations which occur during formation of the SiGe layer and buried oxide layer, heat treatment is performed, followed by the formation of a strained silicon layer over the upper SiGe layer. This technology makes it possible to form a strained silicon layer having a sufficient strain while maintaining a reducing effect of a floating capacity brought by an SOI structure, because the thin SiGe layer (upper side) and the strained silicon layer are formed over the buried oxide layer.
In Japanese Patent Laid-Open No. Hei 10 (1998)-270685, disclosed is a technology of forming a strained silicon layer over a silicon-germanium layer and then forming an MISFET over the strained silicon layer. In this technology, the source region and drain region of the MISFET are formed in the strained layer so that the pn junction between the source region and drain region exists in the strained silicon layer. By this, junction leakage of the MISFET can therefore be prevented.
In Japanese Unexamined Patent Publication No. 2003-110102, disclosed is a technology of improving the power added efficiency of a power amplification MISFET to be used for mobile terminals. Described specifically, the technology disclosed in this document is to form an MISFET by forming a first SiGe layer which is a first conductivity type and has a high impurity concentration, a second SiGe layer which is a first conductivity type and has a low impurity concentration, and a strained Si layer having a low impurity concentration over a silicon substrate in the order of mention and cause a portion of the strained Si layer to serve as a channel region; and forming a source electrode so as to pass through the second SiGe layer having a low impurity concentration and electrically connect to the first SiGe layer having a high impurity concentration or the silicon substrate. A high-density crystal defect region is formed only inside the silicon substrate or the first SiGe layer and the second SiGe layer is prevented from contacting the high-density crystal defect region.